UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1165
UPD70F3786GJ-GAE-AX
Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3786GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Note
Cautions 1. Execute transmission abort processing by clearing the TRQ bit, not the RDY bit.
During a period of a total of 11 bits, 3 bits of interframe space and 8 bits of suspend transmission, the
transmission request may have already been acknowledged by the protocol layer.
transmission may not be aborted but started even if the TRQ bit is cleared.
2. Before making a sleep mode transition request, confirm that there is no transmission
3. The TSTAT bit can be periodically checked by a user application or can be checked after
4. Do not execute a new transmission request including in the other message buffers while
5. If data of the same message buffer are successively transmitted or if only one message
request left using this processing.
the transmit completion interrupt.
transmission abort processing is in progress.
buffer is used, judgments whether transmission has been successfully executed or failed
may contradict. In such a case, make a judgment by using the history information of the
C0TGPT register.
Figure 21-47. Transmission Abort Processing Except for ABT Transmission
Wait for a period of 11 CAN data
be aborted matches C0LOPT
CLEAR_ABTTRG bit = 1
Transmission successful
SET_ABTTRG bit = 0
Read C0LOPT register.
CLEAR_TRQ bit = 1
Clear ABTTRG bit.
ABTTRG bit = 0?
SET_TRQ bit = 0
Message buffer to
TSTAT bit = 0?
Clear TRQ bit.
START
bits.
register?
(Normal Operation Mode with ABT)
END
END
CHAPTER 21 CAN CONTROLLER
Note
Yes
Yes
Yes
Yes
Yes
Yes
User’s Manual U19601EJ2V0UD
No
No
No
No
No
No
Transmit abort request
was successful.
Consequently,
1163
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