UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1216

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1214
Cautions 1. If DMA is enabled while data is being read from the UF0BO2 register in the PIO mode, a
Bit position
3
2
2. If the last data of the FIFO on the CPU side is read in the DMA transfer mode, the DMA
3. If the TC signal is received in the DMA transfer mode, the DMA request signal becomes
DMA request is immediately issued.
request signal becomes inactive.
inactive.
BKO2NK
BKO1NK
Bit name
CHAPTER 22 USB FUNCTION CONTROLLER (USBF)
This bit controls NAK to Endpoint4 (bulk 2 transfer (OUT)).
This bit is set to 1 only when the FIFO connected to the SIE side of the UF0BO2 register
(64-byte FIFO of bank configuration) cannot receive data. It is cleared to 0 when a
toggle operation is performed. The bank is changed (toggle operation) when the
following conditions are satisfied.
FW should be used to read data of the UF0BO2L register when it has received the
BLKO2DT interrupt request and read as many data from the UF0BO2 register as the
value of that data. To not receive data from the USB bus for some reason even if USBF
is ready to receive data, set this bit to 1 by FW. In this case, USBF keeps transmitting
NAK until the FW clears this bit to 0. This bit is also cleared to 0 as soon as the UF0BO2
register has been cleared.
This bit controls NAK to Endpoint2 (bulk 1 transfer (OUT)).
This bit is set to 1 only when the FIFO connected to the SIE side of the UF0BO1 register
(64-byte FIFO of bank configuration) cannot receive data. It is cleared to 0 when a
toggle operation is performed. The bank is changed (toggle operation) when the
following conditions are satisfied.
FW should be used to read data of the UF0BO1L register when it has received the
BLKO1DT interrupt request and read as many data from the UF0BO1 register as the
value of that data. To not receive data from the USB bus for some reason even if USBF
is ready to receive data, set this bit to 1 by FW. In this case, USBF keeps transmitting
NAK until the FW clears this bit to 0. This bit is also cleared to 0 as soon as the UF0BO1
register has been cleared.
1: Transmit NAK.
0: Do not transmit NAK (default value).
• Data correctly received is stored in the FIFO connected to the SIE side.
• The value of the FIFO counter connected to the CPU side is 0 (completion of
1: Transmit NAK.
0: Do not transmit NAK (default value).
• Data correctly received is stored in the FIFO connected to the SIE side.
• The value of the FIFO counter connected to the CPU side is 0 (completion of
reading).
reading).
User’s Manual U19601EJ2V0UD
Function
(2/4)