UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1248
UPD70F3786GJ-GAE-AX
Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3786GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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UF0DMS1
(28) UF0 DMA status 1 register (UF0DMS1)
Remark
Bit position
7, 5, 4, 2
This register indicates the DMA status of Endpoint1 to Endpoint4.
This register is read-only, in 8-bit units.
The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4)
and the current setting of the interface.
Each bit is automatically cleared to 0 when this register is read. Even when this register is read, however, bits
4 and 3 of the UF0IS0 register are not cleared to 0. If the target endpoint is no longer supported by the
SET_INTERFACE request, each bit is automatically cleared to 0 by hardware (however, the DMA_END
interrupt request and Short interrupt request are not cleared).
6, 3
n = 1 to 4
m = 2, 4
DEDE4
7
DEDEn
DSPEm
Bit name
DSPE4
6
CHAPTER 22 USB FUNCTION CONTROLLER (USBF)
DEDE3
These bits indicate that the DMA end (TC) signal for Endpoint n becomes active and
DMA is stopped while a DMA read request is being issued from Endpoint n to memory.
These bits indicate that, although a DMA read request was being issued from Endpoint
m to memory, DMA has been stopped because the received data is a short packet and
there is no more data to be transferred.
5
1: DMA end signal for Endpoint n is active.
0: DMA end signal for Endpoint n is inactive (default value).
1: DMASTOP_EPm signal is active.
0: DMASTOP_EPm signal is inactive (default value).
DEDE2
User’s Manual U19601EJ2V0UD
4
DSPE2
3
DEDE1
2
Function
1
0
0
0
00200050H
Address
After reset
00H
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