UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1368

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Notes 1. Cancel the MAC block software reset by setting the MCRST, RFRST, and TFRST bits of the MACC2
Set the registers of the MAC.
Specify the operating mode
the MAC operating mode.
on the serial management
Execute a software reset
Execute a software reset
Execute a software reset
3. The SFTRST bit of the RSTCNT register clears automatically after being set to 1.
2. Cancel the serial management interface block software reset by setting the MIRST bit of the MIIC
the MII operating mode
the statistics counter.
on the MAC block.
of the FIFO block.
on the FIFO block.
register to 1 simultaneously, then simultaneously clearing them to 0. Leave an interval of at least
5 TXCLK clock cycles between setting and clearing the MCRST, RFRST, and TFRST bits.
register to 1 and then clearing it to 0. Leave an interval of at least 5 Ethernet controller clock (f
cycles between setting and clearing the MIRST bit.
interface block.
MIICTL = 01H
Specify
START
Specify
Clear
A
Figure 23-2. Initializing the Ethernet Controller (1/2)
Set the MIIEN bit of the MIICTL register to 1 to enable operation of the ports related to
the Ethernet controller. Access the MIICTL register in 8-bit units.
Specify the operating mode of the MAC by using the MACC1 and MACC2 registers.
After specifying the operating mode of the MAC, execute a software reset on the MAC block
by using the MCRST, RFRST, and TFRST bits of the MACC2 register
Execute a software reset on the serial management interface block
After executing a software reset on the serial management interface block,
specify the operating mode of the MII by using the MIIC register.
Set the IPGT, IPGR, CLRT, LMAX, LSA1, LSA2, VLPT, AFR, HT1, HT2, CAR1,
and CAR2 registers.
Clear the statistics count register.
Execute a software reset on the FIFO block
After executing a software reset on the FIFO block, specify the operating mode
of the FIFO block by using the MFFCONT register.
by using the MIRST bit of the MIIC register
by using the SFTRST bit of the RSTCNT register
CHAPTER 23 ETHERNET CONTROLLER
User’s Manual U19601EJ2V0UD
Note 2
.
Note 3
.
Note 1
.
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