UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 18

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 21 CAN CONTROLLER ................................................................................................... 1027
16
20.7 I
20.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control ...................... 1000
20.9 Address Match Detection Method ...................................................................................... 1002
20.10 Error Detection ..................................................................................................................... 1002
20.11 Extension Code .................................................................................................................... 1002
20.12 Arbitration ............................................................................................................................. 1003
20.13 Wakeup Function ................................................................................................................. 1004
20.14 Communication Reservation .............................................................................................. 1005
20.15 Cautions ................................................................................................................................ 1010
20.16 Communication Operations ................................................................................................ 1011
20.17 Timing of Data Communication .......................................................................................... 1020
21.1 Overview ............................................................................................................................... 1027
21.2 CAN Protocol ........................................................................................................................ 1030
21.3 Functions .............................................................................................................................. 1041
21.4 Connection with Target System ......................................................................................... 1053
21.5 Internal Registers of CAN Controller ................................................................................. 1054
20.6.4
20.6.5
20.6.6
20.6.7
20.7.1
20.7.2
20.7.3
20.7.4
20.7.5
20.7.6
20.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) .......................1005
20.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1) ......................1009
20.16.1 Master operation in single master system ...............................................................................1012
20.16.2 Master operation in multimaster system ..................................................................................1013
20.16.3 Slave operation........................................................................................................................1016
21.1.1
21.1.2
21.1.3
21.2.1
21.2.2
21.2.3
21.2.4
21.2.5
21.3.1
21.3.2
21.3.3
21.3.4
21.3.5
21.3.6
21.3.7
2
C Interrupt Request Signals (INTIICn).................................................................................980
ACK ...........................................................................................................................................975
Stop condition............................................................................................................................976
Wait state ..................................................................................................................................977
Wait state cancellation method..................................................................................................979
Master device operation ............................................................................................................980
Slave device operation (when receiving slave address data (address match))..........................983
Slave device operation (when receiving extension code) ..........................................................987
Operation without communication .............................................................................................990
Arbitration loss operation (operation as slave after arbitration loss) ..........................................991
Operation when arbitration loss occurs (no communication after arbitration loss) .....................993
Features ..................................................................................................................................1027
Overview of functions ..............................................................................................................1028
Configuration ...........................................................................................................................1029
Frame format ...........................................................................................................................1030
Frame types.............................................................................................................................1031
Data frame and remote frame..................................................................................................1031
Error frame ..............................................................................................................................1039
Overload frame........................................................................................................................1040
Determining bus priority...........................................................................................................1041
Bit stuffing................................................................................................................................1041
Multi masters ...........................................................................................................................1041
Multi cast .................................................................................................................................1041
CAN sleep mode/CAN stop mode function..............................................................................1042
Error control function ...............................................................................................................1042
Baud rate control function........................................................................................................1049
User’s Manual U19601EJ2V0UD