UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 322
UPD70F3786GJ-GAE-AX
Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3786GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Note The overflow counter is set arbitrarily by software on the internal RAM.
<1> Read the TAAnCCRm register (setting of the default value of the TIAAnm pin input).
<2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow
<3> An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag
<4> Read the TAAnCCRm register.
Remark
TAAnCCRm register
INTTAAnOV signal
interrupt servicing.
to 0 in the overflow interrupt servicing.
Read the overflow counter.
→ When the overflow counter is “N”, the pulse width can be calculated by (N × 10000H + D
Clear the overflow counter (0H).
TIAAnm pin input
D
In this example, the pulse width is (20000H + D
16-bit counter
TAAnOVF bit
m0
TAAnCE bit
m = 0, 1
n = 0 to 5
counter
).
Overflow
FFFFH
0000H
Note
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Example when capture trigger interval is long
User’s Manual U19601EJ2V0UD
0H
D
m0
<1> <2>
m1
1 cycle of 16-bit counter
– D
m0
Pulse width
) because an overflow occurs twice.
D
1H
m0
<3> <4>
D
m1
2H 0H
D
m1
m1
–
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