UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 436

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

434
(b) Pulse width measurement with capture register
When pulse width measurement is performed with the TABnCCRm register used as a capture register,
software processing is necessary for reading the capture register each time the INTTABnCCm signal has
been detected and for calculating an interval.
Note The V850ES/JH3-E only includes the TIAB13 pin; it is not provided with the TIAB03 pin. When
Remark
using the V850ES/JH3-E, the TAB0CCR3 register and the INTTAB0CCR3 signal cannot be
used.
INTTABnCC3 signal
TABnCCR3 register
INTTABnCC0 signal
TABnCCR0 register
INTTABnCC1 signal
INTTABnCC2 signal
TABnCCR1 register
TABnCCR2 register
TIABn3 pin input
INTTABnOV signal
n = 0, 1
TIABn0 pin input
TIABn1 pin input
TIABn2 pin input
16-bit counter
TABnOVF bit
TABnCE bit
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
FFFFH
0000H
Note
Note
Note
Pulse interval
(D
Pulse interval
(D
20
Pulse interval
Pulse interval
0000
0000
0000
0000
00
+ 1)
(D
(D
+ 1)
D
30
10
20
D
+ 1)
+ 1)
User’s Manual U19601EJ2V0UD
00
D
Pulse interval
30
D
(10000H +
D
10
D
01
Pulse interval
Pulse interval
Cleared to 0 by
CLR instruction
(10000H +
Pulse interval
00
(10000H +
− D
D
D
(10000H +
D
11
21
D
00
31
D
− D
D
− D
20
)
01
10
− D
D
10
30
20
)
D
)
30
Pulse interval
11
)
D
(10000H +
D
Pulse interval
21
02
(10000H +
D
D
D
− D
12
31
01
− D
Cleared to 0 by
CLR instruction
D
01
Pulse interval
11
)
(10000H +
11
D
D
)
32
12
Pulse interval
D
D
− D
(20000H +
Pulse interval
31
02
D
(D
22
31
Pulse interval
D
D
13
D
)
− D
(10000H +
21
D
12
32
− D
D
03
21
13
D
− D
12
)
CLR instruction
Cleared to 0 by
02
)
Pulse interval
02
(10000H +
D
)
D
33
03
D
Pulse interval
− D
D
22
(D
32
32
23
D
D
)
13
− D
D
33
D
22
D
23
22
03
)
D
33
D
23