UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 738

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

736
(1) UARTBn control register 0 (UBnCTL0)
(2) UARTBn status register (UBnSTR)
(3) UARTBn control register 2 (UBnCTL2)
(4) UARTBn FIFO control register 0 (UBnFIC0)
(5) UARTBn FIFO control register 1 (UBnFIC1)
(6) UARTBn FIFO control register 2 (UBnFIC2)
(7) UARTBn FIFO status register 0 (UBnFIS0)
(8) UARTBn FIFO status register 1 (UBnFIS1)
(9) Receive shift register
This register controls the transfer operation of UARTBn.
This register indicates the transfer status during transmission and the contents of a reception error. The
status flag of this register, which indicates the transfer status during transmission, indicates the data retention
status of the transmit shift register and the transmit data register (the UBnTX register in the single mode or
transmit FIFO in the FIFO mode). Each reception error flag is set to 1 when a reception error occurs, and
cleared to 0 when 0 is written to the UBnSTR register.
This register is used to specify the division ratio by which to control the baud rate (serial transfer speed) of
UARTBn.
This register is used to select the operation mode of UARTBn, clear the transmit FIFO/receive FIFO that
becomes valid in the FIFO mode, and specify the timing mode in which the transmission enable interrupt
request signal (INTUBnTIT)/reception end interrupt request signal (INTUBnTIR) occurs.
This register is valid in the FIFO mode.
(INTUBnTITO) if data is stored in the receive FIFO when the next data does not come (start bit is not
detected) even after the reception wait time of the next data has elapsed after the stop bit has been received.
This register is valid in the FIFO mode. It is used to set the timing to generate the transmission enable
interrupt request signal (INTUBnTIT)/reception end interrupt request signal (INTUBnTIR), using the number of
data transmitted or received as a trigger.
This register is valid in the FIFO mode. The number of bytes of data stored in the receive FIFO can be read
from this register.
This register is valid in the FIFO mode. The number of empty bytes of the transmit FIFO can be read from
this register.
This is a shift register that converts the serial data that was input to the RXDBn pin into parallel data. One
byte of data is received, and if a stop bit is detected, the received data is transferred to the receive data
register.
This register cannot be directly manipulated.
Remark
n = 0, 1
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
User’s Manual U19601EJ2V0UD
It generates a reception timeout interrupt request signal