UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 761
UPD70F3786GJ-GAE-AX
Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3786GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Company:
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
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20 000
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(2) Reception end interrupt request signal (INTUBnTIR)
(3) Transmission enable interrupt request signal (INTUBnTIT)
(4) FIFO transmission end interrupt request signal (INTUBnTIF)
(a) Single mode
(b) FIFO mode
(a) Single mode
(b) FIFO mode
(a) Single mode
(b) FIFO mode
When reception is enabled, a reception end interrupt request signal is generated if data is shifted into the
receive shift register and stored in the UBnRX register (if the receive data can be read).
When reception is disabled, no reception end interrupt request signal is generated.
When reception is enabled, a reception end interrupt request signal is generated if data is shifted into the
receive shift register and receive data of the number set as the trigger by the UBnFIC2.UBnRT3 to
UBnFIC2.UBnRT0 bits is transferred to receive FIFO (if receive data of the specified number can be
read).
When reception is disabled, no reception end interrupt request signal is generated.
The transmission enable interrupt request signal is generated if transmit data of one frame, including 7 or
8 bits of characters, is shifted out from the transmit shift register and the UBnTX register becomes empty
(if transmit data can be written).
The transmission enable interrupt request signal is generated if transmit data of the number set as the
trigger by the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits is transferred to the transmit shift register from
transmit FIFO (if transmit data of the specified number can be written).
Cannot be used.
The FIFO transmission end interrupt request signal is generated when no more data is in transmit FIFO
and the transmit shift register (when the FIFO and register become empty). After the FIFO transmission
end interrupt request signal has occurred, clear the interrupt request signal (INTUBnTIT) held pending in
the pending mode (UBnFIC0.UBnITM bit = 0) by clearing the FIFO (UBnFIC0.UBnTFC bit = 1).
Caution If the FIFO transmission end interrupt request signal is generated (all transmit data are
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
not transmitted) because writing the next transmit data to transmit FIFO is delayed, do
not clear the FIFO.
User’s Manual U19601EJ2V0UD
759
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