UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 772

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.7.4 Receive operation
UBnCTL0.UBnRXE bit to 1. RXDBn pin sampling begins and a start bit is detected. When the start bit is detected,
the receive operation begins, and data is stored sequentially in the receive shift register according to the baud rate
that was set.
each time the reception of one frame of data is completed. Normally, the receive data is transferred from the UBnRX
register to memory by this interrupt servicing.
number set as the trigger by the UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits are transferred to receive FIFO.
number set as the trigger by the UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits can be read from receive FIFO.
stored in receive FIFO (0 bytes or more) can be read from receive FIFO by referencing the number of receive data
specified as the trigger by the UBnRT3 to UBnRT0 bits (1 byte) or the UBnFIS0 register.
770
The awaiting reception state is set by setting the UBnCTL0.UBnPWR bit to 1 and then setting the
In the single mode (UBnFIC0.UBnMOD bit = 0), a reception end interrupt request signal (INTUBnTIR) is generated
In the FIFO mode (UBnFIC0.UBnMOD bit = 1), the INTUBnTIR signal occurs when as many receive data as the
If the pending mode is specified (UBnFIC0.UBnIRM bit = 0) in the FIFO mode, as many receive data as the
If the pointer mode is specified (UBnFIC0.UBnIRM bit = 1) in the FIFO mode, as many data as the number of bytes
Caution If the pointer mode is specified in the FIFO mode and if as many data as the number of bytes
(1) Reception enabled state
(2) Starting a receive operation
Remark
This state is set by the UBnCTL0.UBnRXE bit.
• UBnRXE = 1: Reception enabled state
• UBnRXE = 0: Reception disabled state
However, because this bit is also used by CSIFm, enable reception after setting the CFmCTL0.CFmPWR bit
to 0 and disabling the CSIFm operation (m = 3, 4).
In the reception disabled state, the reception hardware stands by in the initial state. At this time, the
reception end interrupt request signal or reception error interrupt request signal does not occur, and the
contents of the receive data register (UBnRX register in the single mode or receive FIFO in the FIFO mode
(UBnRXAP register)) are retained.
A receive operation is started by the detection of a start bit.
The RXDBn pin is sampled using the serial clock from UARTBn control register 2 (UBnCTL2).
stored in receive FIFO are read by referencing the UBnFIS0 register, no data may be stored in
receive FIFO (UBnFIS0.UBnRB4 to UBnFIS0.UBnRB0 bits = 00000) even though the reception
end interrupt request signal (INTUBnTIR) has occurred. In this case, do not read data from
receive FIFO. Be sure to read data from receive FIFO after confirming that the number of bytes
stored in receive FIFO = 1 byte or more (UBnRB4 to UBnRB0 bits = other than 00000).
n = 0, 1
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
User’s Manual U19601EJ2V0UD