UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 943
UPD70F3786GJ-GAE-AX
Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3786GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Notes 1. The INTCFnT interrupt is set when the data written to the CFnTX register is transferred to the data
Caution In single transfer mode, writing to the CFnTX register with the CFnTSF bit set to 1 is ignored.
Remark
2. The INTCFnR interrupt occurs if reception is correctly ended and receive data is ready in the CFnRX
SCKFn pin
SCKFn pin
SIFn capture
Reg-R/W
INTCFnT
interrupt
SIFn capture
SOFn pin
Reg-R/W
INTCFnT
interrupt
SOFn pin
INTCFnR
interrupt
CFnTSF bit
INTCFnR
interrupt
CFnTSF bit
shift register in the continuous transmission or continuous transmission/reception modes. In the
single transmission or single transmission/reception modes, the INTCFnT interrupt request signal is
not generated, but the INTCFnR interrupt request signal is generated upon end of communication.
register while reception is enabled. In the single mode, the INTCFnR interrupt request signal is
generated even in the transmission mode, upon end of communication.
This has no effect on the operation during transfer.
For example, if the next data is written to the CFnTX register when DMA is started by
generating the INTCFnR signal, the written data is not transferred because the CFnTSF bit is
set to 1.
Use the continuous transfer mode, not the single transfer mode, for such applications.
n = 0 to 4 (V850ES/JH3-E)
n = 0 to 6 (V850ES/JJ3-E)
Note 1
Note 1
Note 2
Note 2
(iii) Communication type 2 (CFnCKP and CFnDAP bits = 01)
(iv) Communication type 4 (CFnCKP and CFnDAP bits = 11)
CHAPTER 19 CLOCKED SERIAL INTERFACE F (CSIF)
D7
D7
User’s Manual U19601EJ2V0UD
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
(2/2)
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