SAK-TC1797-512F180E AC Infineon Technologies, SAK-TC1797-512F180E AC Datasheet - Page 184

• Manufacturer Part Number: SAK-TC1797-512F180E AC
• Description: IC MCU 32BIT FLASH 416-BGA
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1797-512F180E AC

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 180MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 219
• Program Memory Size: 4MB (4M x 8)
• Program Memory Type: FLASH
• Ram Size: 224K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 48x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 180.0 MHz
• Sram (incl. Cache): 224.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 48
• Program Memory: 4.0 MB
• For Use With: B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: SP000432392

5.3.11.4 E-Ray Interface Timing
The timings in this section are valid for the strong / sharp and strong / medium settings
of the output drivers, and for both A1 or A2 input pads. The timing parameters are not
subject to production test, but verified by design / characterization.
Table 32
Parameter
TxDA / TxDB Signal Timing at end of frame
Time span from last
BSS to FES without the
influence of quartz
tolerances d10Bit_Tx
TxD data valid, from
f
⇒ TxDA, TxDB,
(dTxAsym)
RxDA / RxDB Signal Timing at end of frame
Time span between last
BSS and FES that is
properly decoded,
without influence of
quartz tolerances
d10Bit_Rx
RxD capture by
RxDA / RxDB ⇒
sampling flip-flop,
(dRxAsym)
1) PLL jitter included.
2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers.
3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of |
4)Limits of 966.5 ns and 1046 ns correspond to (30%, 70%) ×
input thresholds.
Due to different input thresholds of the TC1797, a correcton of -0.5 ns and +0.1 ns has
been applied.
Data Sheet
sample
Quartz tolerance and PLL jitter are not included.
flip-flop txd_reg
1) 4) 5)
2) 3)
5)
E-Ray Interface Timing (Operating Conditions apply)
f
sample
1)
,
Symbol
t
|t
t
|t
60
63
61
64
-
-
t
t
62
65
| CC –
| CC –
CC 997.75 –
SR 966
Min.
180
Limit Values
Typ. Max.
–
–
–
1002.25 ns
1.5
1046.1
3.0
t
V
F
DDP
-
Electrical Parameters
Unit Notes
ns
ns
ns
t
R
| ≤ 1 ns.
FlexRay standard
, C
Conditions
f
f
C
(TxDA, TXDB)
Asymmetrical
delay of rising
and falling edge
(TxDA, TxDB)
f
f
C
(TxDA, TXDB)
Asymmetrical
delay of rising
and falling edge
(RxDA, RxDB)
L
oscdd
oscdd
oscdd
oscdd
L
L
= 25 pF
= 25 pF
= 25 pF
V1.1, 2009-04
= 40MHz;
= 20MHz;
= 20MHz;
= 40MHz;
TC1797