ATMEGA163L-4AI Atmel, ATMEGA163L-4AI Datasheet - Page 80
ATMEGA163L-4AI
Manufacturer Part Number
ATMEGA163L-4AI
Description
IC AVR MCU 16K A/D 2.7V 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA163-8AC.pdf
(187 pages)
Specifications of ATMEGA163L-4AI
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Price
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Manufacturer:
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Two-wire Serial
Interface (Byte
Oriented)
80
ATmega163(L)
The Two-wire Serial Interface supports bi-directional serial communication. It is
designed primarily for simple but efficient integrated circuit (IC) control. The system is
comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information
between the ICs connected to them. Various communication configurations can be
designed using this bus. Figure 49 shows a typical Two-wire Serial Bus configuration.
Any device connected to the bus can be master or slave. Note that all AVR devices con-
nected to the bus must be powered to allow any bus operation.
Figure 49. Two-wire Serial Bus Configuration
The Two-wire Serial Interface supports Master/Slave and Transmitter/Receiver opera-
tion at up to 217 kHz bus clock rate. The Two-wire Serial Interface has hardware
support for 7-bit addressing, but is easily extended to, e.g., a 10-bit addressing format in
software. When the Two-wire Serial Interface is enabled (TWEN in TWCR is set), a
glitch filter is enabled for the input signals from the pins PC0 (SCL) and PC1 (SDA), and
the output from these pins is slew-rate controlled. The Two-wire Serial Interface is byte
oriented. The operation of the Two-wire Serial Bus is shown as a pulse diagram in Fig-
ure 50, including the START and STOP conditions and generation of ACK signal by the
bus receiver.
Figure 50. Two-wire Serial Bus Timing Diagram
The block diagram of the Two-wire Serial Interface is shown in Figure 51.
SDA
SCL
CONDITION
START
Device 1
MSB
1
2
Device 2
7
R/W
BIT
8
Device 3
ACK
9
FROM RECEIVER
ACKNOWLEDGE
.......
1
2
Device n
8
ACK
9
R1
R2
STOP CONDITION
REPEATED START
CONDITION
1142E–AVR–02/03
V
SCL
SDA
CC
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