ATMEGA161L-4AI Atmel, ATMEGA161L-4AI Datasheet - Page 54
ATMEGA161L-4AI
Manufacturer Part Number
ATMEGA161L-4AI
Description
IC AVR MCU 16K LV 4MZ IND 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA161-8AC.pdf
(159 pages)
Specifications of ATMEGA161L-4AI
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Other names
ATMEGA161L4AI
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Manufacturer
Quantity
Price
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Timer/Counter1 Output
Compare Register – OCR1AH
AND OCR1AL
Timer/Counter1 Output
Compare Register – OCR1BH
AND OCR1BL
Timer/Counter1 Input Capture
Register – ICR1H AND ICR1L
54
ATmega161(L)
The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read
and write access. If Timer/Counter1 is written to and a clock source is selected, the
Timer/Counter1 continues counting in the timer clock cycle after it is preset with the writ-
ten value.
The Output Compare Registers are 16-bit read/write registers.
The Timer/Counter1 Output Compare Registers contain the data to be continuously
compared with Timer/Counter1. Actions on compare matches are specified in the
Timer/Counter1 Control and Status Registers. A software write to the Timer/Counter
Register blocks compare matches in the next Timer/Counter clock cycle. This prevents
immediate interrupts when initializing the Timer/Counter.
A compare match will set the Compare Interrupt Flag in the CPU clock cycle following
the compare event.
Since the Output Compare Registers (OCR1A and OCR1B) are 16-bit registers, a tem-
porary register (TEMP) is used when OCR1A/B are written to ensure that both bytes are
updated simultaneously. When the CPU writes the High byte, OCR1AH or OCR1BH,
the data is temporarily stored in the TEMP Register. When the CPU writes the Low byte,
OCR1AL or OCR1BL, the TEMP Register is simultaneously written to OCR1AH or
OCR1BH. Consequently, the High byte OCR1AH or OCR1BH must be written first for a
full 16-bit register write operation.
The TEMP Register is also used when accessing TCNT1 and ICR1. If the main program
and interrupt routines perform access to registers using TEMP, interrupts must be dis-
abled during access from the main program and interrupt routines.
Bit
$2B ($4B)
$2A ($4A)
Read/Write
Initial Value
Bit
$29 ($49)
$28 ($48)
Read/Write
Initial Value
Bit
$25 ($45)
$24 ($44)
Read/Write
Initial Value
MSB
MSB
R/W
R/W
R/W
R/W
MSB
15
15
7
0
0
15
7
0
0
R
R
7
0
0
R/W
R/W
R/W
R/W
14
14
6
0
0
6
0
0
14
R
R
6
0
0
R/W
R/W
R/W
R/W
13
13
5
0
0
5
0
0
13
R
R
5
0
0
R/W
R/W
R/W
R/W
12
12
4
0
0
0
4
0
12
R
R
4
0
0
R/W
R/W
R/W
R/W
11
11
3
0
0
3
0
0
11
R
R
3
0
0
R/W
R/W
R/W
R/W
10
2
0
0
10
2
0
0
10
R
R
2
0
0
R/W
R/W
R/W
R/W
9
1
0
0
9
1
0
0
R
R
9
1
0
0
LSB
R/W
R/W
LSB
R/W
R/W
8
0
0
0
8
0
0
0
LSB
1228D–AVR–02/07
R
R
8
0
0
0
OCR1BH
OCR1BL
OCR1AH
OCR1AL
ICR1H
ICR1L
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