ATMEGA323L-4AI Atmel, ATMEGA323L-4AI Datasheet - Page 125
ATMEGA323L-4AI
Manufacturer Part Number
ATMEGA323L-4AI
Description
IC AVR MCU 32K LV 4MZ IND 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA323L-4PC.pdf
(247 pages)
Specifications of ATMEGA323L-4AI
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA323L4AI
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The Analog Comparator
Control and Status Register –
ACSR
1457G–AVR–09/03
• Bit 7 – ACD: Analog Comparator Disable
When this bit is set(one), the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power con-
sumption in active and idle mode. When changing the ACD bit, the Analog Comparator
Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can
occur when the bit is changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap voltage of nominally 1.22 ± 0.10V replaces the pos-
itive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the
positive input of the Analog Comparator. See “Internal Voltage Reference” on page 31.
• Bit 5 – ACO: Analog Comparator Output
ACO is directly connected to the comparator output.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE
bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, ACI is cleared by
writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the ana-
log comparator interrupt is activated. When cleared (zero), the interrupt is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When set (one), this bit enables the Input Capture function in Timer/Counter1 to be trig-
gered by the Analog Comparator. The comparator output is in this case directly
connected to the Input Capture Front-end Logic, making the comparator utilize the noise
canceler and edge select features of the Timer/Counter1 Input Capture Interrupt. When
cleared (zero), no connection between the Analog Comparator and the Input Capture
function is given. To make the comparator trigger the Timer/Counter1 Input Capture
Interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one).
Bit
$08 ($28)
Read/Write
Initial Value
ACD
R/W
7
0
ACBG
R/W
6
0
ACO
N/A
R
5
R/W
ACI
4
0
ACIE
R/W
3
0
ACIC
R/W
2
0
ATmega323(L)
ACIS1
R/W
1
0
ACIS0
R/W
0
0
ACSR
125
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