ATMEGA323L-4AI Atmel, ATMEGA323L-4AI Datasheet - Page 98
ATMEGA323L-4AI
Manufacturer Part Number
ATMEGA323L-4AI
Description
IC AVR MCU 32K LV 4MZ IND 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA323L-4PC.pdf
(247 pages)
Specifications of ATMEGA323L-4AI
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA323L4AI
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USART Baud Rate Registers –
UBRRL and UBRRHs
98
ATmega323(L)
• Bit 2:1 – UCSZ1:0: Character Size
The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits
(character size) in a frame the Receiver and Transmitter uses.
Table 35. Character Size
• Bit 0 – UCPOL: Clock Polarity
This bit is used for synchronous mode only. Set this bit to zero when asynchronous
mode is used. The UCPOL bit sets the relationship between data output change and
data input sample, and the synchronous clock (XCK).
The UBRRH Register shares the same I/O location as the UCSRC Register. See the
“Accessing UBRRH/UCSRC Registers” on page 92 section which describes how to
access this register.
• Bit 15 – URSEL: Register Select
This bit selects between accessing the UBRRH or the UCSRC Register. It is read as
zero when reading UBRRH. The URSEL must be zero when writing the UBRRH.
• Bit 14:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit
must be set to zero when UBRRH is written.
Bit
$20 ($40)
$09 ($29)
Read/Write
Initial Value
UCPOL
0
1
UCSZ2
0
0
0
0
1
1
1
1
URSEL
Transmitted Data Changed (Output
of TxD Pin)
Falling XCK Edge
Rising XCK Edge
R/W
R/W
15
7
0
0
R/W
14
R
–
6
0
0
UCSZ1
0
0
1
1
0
0
1
1
R/W
13
R
–
5
0
0
R/W
12
R
–
4
0
0
UBRR[7:0]
UCSZ0
0
1
0
1
0
1
0
1
R/W
R/W
11
3
0
0
Received Data Sampled (Input on
RxD Pin)
Rising XCK Edge
Falling XCK Edge
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
R/W
R/W
10
2
0
0
UBRR[11:8]
R/W
R/W
9
1
0
0
R/W
R/W
1457G–AVR–09/03
8
0
0
0
UBRRH
UBRRL
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