AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 131
AT89C51SND2C-7FTUL
Manufacturer Part Number
AT89C51SND2C-7FTUL
Description
IC 8051 MCU FLASH 64K MP3 100BGA
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51SND2C-7FTUL.pdf
(242 pages)
Specifications of AT89C51SND2C-7FTUL
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
Peripherals
Audio, I²S, MP3, PCM, POR, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b; D/A 2x20b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Data Bus Width
8 bit
Data Ram Size
2.25 KB
Interface Type
ATAPI, I2S, IDE, SPI, UART, USB
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT89C51SND2C7FTUL
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17. IDE/ATAPI Interface
17.1
4341H–MP3–10/07
Description
The AT8xC51SND2C provides an IDE/ATAPI interface allowing connection of devices such as
CD-ROM reader, CompactFlash cards, Hard Disk Drive, etc. It consists of a 16-bit data transfer
(read or write) between the AT8xC51SND2C and the IDE device.
The IDE interface mode is enabled by setting the EXT16 bit in AUXR (see Figure 7-5, page 29).
As soon as this bit is set, all MOVX instructions read or write are done in a 16-bit mode compare
to the standard 8-bit mode. P0 carries the low order multiplexed address and data bus (A7:0,
D7:0) while P2 carries the high order multiplexed address and data bus (A15:8, D15:8). When
writing data in IDE mode, the ACC contains D7:0 data (as in 8-bit mode) while DAT16H register
(see Table 17-2) contains D15:8 data. When reading data in IDE mode, D7:0 data is returned in
ACC while D15:8 data is returned in DAT16H.
Figure 17-1 shows the IDE read bus cycle while Figure 17-2 shows the IDE write bus cycle. For
simplicity, these figures depict the bus cycle waveforms in idealized form and do not provide pre-
cise timing information. For IDE bus cycle timing parameters refer to the Section “AC
Characteristics”.
IDE cycle takes 6 CPU clock periods which is equivalent to 12 oscillator clock periods in stan-
dard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode, refer to
the Section “X2 Feature”, page 14.
Slow IDE devices can be accessed by stretching the read and write cycles. This is done using
the M0 bit in AUXR. Setting this bit changes the width of the RD and WR signals from 3 to 15
CPU clock periods.
Figure 17-1. IDE Read Waveforms
Notes:
1.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 out-
CPU Clock
RD
puts SFR content instead of DPH.
RD
signal may be stretched using M0 bit in AUXR register.
ALE
P0
P2
(1)
P2
DPH or P2
DPL or Ri
(2),(3)
AT8xC51SND2C/MP3B
D15:8
D7:0
P2
131
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