AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 153
AT89C51SND2C-7FTUL
Manufacturer Part Number
AT89C51SND2C-7FTUL
Description
IC 8051 MCU FLASH 64K MP3 100BGA
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51SND2C-7FTUL.pdf
(242 pages)
Specifications of AT89C51SND2C-7FTUL
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
Peripherals
Audio, I²S, MP3, PCM, POR, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b; D/A 2x20b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Data Bus Width
8 bit
Data Ram Size
2.25 KB
Interface Type
ATAPI, I2S, IDE, SPI, UART, USB
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT89C51SND2C7FTUL
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
AT89C51SND2C-7FTUL
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4341H–MP3–10/07
Table 18-12. MMINT Register
MMINT (S:E7h Read Only) – MMC Interrupt Register
Reset Value = 0000 0011b
Bit Number
MCBI
7
7
6
5
4
3
2
1
0
Mnemonic
EORI
MCBI
EORI
EOCI
EOFI
F2EI
F1EI
F2FI
F1FI
Bit
6
Description
MMC Card Busy Interrupt Flag
Set by hardware when the card enters or exits its busy state (when the busy signal is
asserted or deasserted on the data line).
Cleared when reading MMINT.
End of Response Interrupt Flag
Set by hardware at the end of response reception.
Cleared when reading MMINT.
End of Command Interrupt Flag
Set by hardware at the end of command transmission.
Clear when reading MMINT.
End of Frame Interrupt Flag
Set by hardware at the end of frame (stream or block) transfer.
Clear when reading MMINT.
FIFO 2 Full Interrupt Flag
Set by hardware when second FIFO becomes full.
Cleared by hardware when second FIFO becomes empty.
FIFO 1 Full Interrupt Flag
Set by hardware when first FIFO becomes full.
Cleared by hardware when first FIFO becomes empty.
FIFO 2 Empty Interrupt Flag
Set by hardware when second FIFO becomes empty.
Cleared by hardware when second FIFO becomes full.
FIFO 1 Empty Interrupt Flag
Set by hardware when first FIFO becomes empty.
Cleared by hardware when first FIFO becomes full.
EOCI
5
EOFI
4
F2FI
AT8xC51SND2C/MP3B
3
F1FI
2
F2EI
1
F1EI
0
153
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