AT87C52X2-3CSUL Atmel, AT87C52X2-3CSUL Datasheet - Page 22
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AT87C52X2-3CSUL
Manufacturer Part Number
AT87C52X2-3CSUL
Description
IC 8051 MCU 8K OTP 30MHZ 40DIP
Manufacturer
Atmel
Series
87Cr
Datasheet
1.TS87C52X2-VCA.pdf
(55 pages)
Specifications of AT87C52X2-3CSUL
Core Processor
8051
Core Size
8-Bit
Speed
30/20MHz
Connectivity
UART/USART
Peripherals
POR
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
UART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Interrupt System
Figure 9. Interrupt Control System
22
EXF2
INT0
INT1
TF0
TF1
TF2
TS8xCx2X2
RI
TI
Individual Enable
IE0
IE1
The TS80C52X2 has a total of 6 interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (timers 0, 1 and 2) and the serial port interrupt. These inter-
rupts are shown in Figure 9.
Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in the Interrupt Enable register (See Table 12.). This register also contains a
global disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority lev-
els by setting or clearing a bit in the Interrupt Priority register (See Table 13.) and in the
Interrupt Priority High register (See Table 14.). shows the bit values and priority levels
associated with each combination.
Table 11. Priority Level Bit Values
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of higher priority level is serviced. If interrupt requests of the same priority level
IPH.x
IPH, IP
0
0
1
1
3
0
3
0
3
0
3
0
3
0
3
0
Global Disable
IP.x
0
1
0
1
High priority
interrupt
Interrupt
polling
sequence, decreasing from
high to low priority
Low priority
interrupt
Interrupt Level Priority
3 (Highest)
0 (Lowest)
1
2
4184G–8051–09/06