AT87C52X2-3CSUL Atmel, AT87C52X2-3CSUL Datasheet - Page 8
![IC 8051 MCU 8K OTP 30MHZ 40DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
AT87C52X2-3CSUL
Manufacturer Part Number
AT87C52X2-3CSUL
Description
IC 8051 MCU 8K OTP 30MHZ 40DIP
Manufacturer
Atmel
Series
87Cr
Datasheet
1.TS87C52X2-VCA.pdf
(55 pages)
Specifications of AT87C52X2-3CSUL
Core Processor
8051
Core Size
8-Bit
Speed
30/20MHz
Connectivity
UART/USART
Peripherals
POR
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
UART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
TS80C52X2
Enhanced Features
X2 Feature
Description
8
TS8xCx2X2
In comparison to the original 80C52, the TS80C52X2 implements some new features,
which are
•
•
•
•
•
•
•
The TS80C52X2 core needs only 6 clock periods per machine cycle. This feature called
”X2” provides the following advantages:
•
•
•
•
In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
The clock for the whole circuit and peripheral is first divided by two before being used by
the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1
input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic
ratio between 40 to 60%. Figure 1. shows the clock generation block diagram. X2 bit is
validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD
mode. Figure 2 shows the mode switching waveforms.
Figure 1. Clock Generation Diagram
XTAL1
The X2 option
The Dual Data Pointer
The 4 level interrupt priority system
The power-off flag
The ONCE mode
The ALE disabling
Some enhanced features are also located in the UART and the Timer 2
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power
Save power consumption while keeping same CPU power (oscillator power saving)
Save power consumption by dividing dynamically operating frequency by 2 in
operating and idle modes
Increase CPU power by 2 while keeping same crystal frequency
:
F
XTAL
2
XTAL1:2
CKCON reg
X2
0
1
F
OSC
CPU control
state machine: 6 clock cycles.
4184G–8051–09/06