AT91SAM7SE512-CU Atmel, AT91SAM7SE512-CU Datasheet - Page 122
AT91SAM7SE512-CU
Manufacturer Part Number
AT91SAM7SE512-CU
Description
IC ARM7 MCU FLASH 512K 144-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE512-CU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
EBI, SPI, TWI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
AT91SAM7SE512-CJ
AT91SAM7SE512-CJ
AT91SAM7SE512-CJ
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7SE512-CU
Manufacturer:
ALTERA
Quantity:
200
Part Number:
AT91SAM7SE512-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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20.2.4.2
Table 20-5.
122
Step
1
2
3
4
5
6
7
8
9
10
11
12
13
SAM7SE512/256/32 Preliminary
Programmer Action
Sets MODE and DATA signals
Clears NCMD signal
Waits for RDY low
Sets DATA signal in tristate
Clears NOE signal
Waits for NVALID low
Reads value on DATA Bus
Sets NOE signal
Waits for NVALID high
Sets DATA in output mode
Sets NCMD signal
Waits for RDY high
Read Handshaking
Read Handshake
For details on the read handshaking sequence, refer to
Figure 20-3.
MODE[3:0]
DATA[15:0]
NVALID
NCMD
Parallel Programming Timing, Read Sequence
NOE
RDY
1
Device Action
Waits for NCMD low
Latch MODE and DATA
Clears RDY signal
Waits for NOE Low
Sets DATA bus in output mode and outputs
the flash contents.
Clears NVALID signal
Waits for NOE high
Sets DATA bus in input mode
Sets NVALID signal
Waits for NCMD high
Sets RDY signal
2
Adress IN
ADDR
3
4
5
Z
6
Figure 20-3
7
Data OUT
8
9
and
DATA I/O
Input
Input
Input
Input
Tristate
Output
Output
Output
Output
X
Input
Input
Input
10
11
Table
X
12
6222F–ATARM–14-Jan-11
20-5.
13
IN
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