AT32UC3A0512-ALUR Atmel, AT32UC3A0512-ALUR Datasheet - Page 57
AT32UC3A0512-ALUR
Manufacturer Part Number
AT32UC3A0512-ALUR
Description
MCU 32BIT 512KB FLASH 144-LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0512-ALUR
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Price
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Part Number:
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O s c 1
c lo c k
O s c 0
13.5.4.1
32058J–AVR32–04/11
c lo c k
P L L O S C
0
1
Enabling the PLL
D iv id e r
P L L D I V
I n p u t
divide the output of the PLL by two and bring the clock in range of the max frequency of the
CPU.
When the PLL is switched on, or when changing the clock source or multiplication factor for the
PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital
logic is automatically masked when the PLL is unlocked, to prevent connected digital logic from
receiving a too high frequency and thus become unstable.
Figure 13-3. PLL with control logic and filters
PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1
as clock source. The PLLMUL and PLLDIV bitfields must be written with the multiplication and
division factors, respectively, creating the voltage controlled ocillator frequency f
frequency f
If PLLOPT[1] field is set to 0:
If PLLOPT[1] field is set to 1:
The PLLn:PLLOPT field should be set to proper values according to the PLL operating fre-
quency. The PLLOPT field can also be set to divide the output frequency of the PLLs by 2.
The lock signal for each PLL is available as a LOCKn flag in POSCSR. An interrupt can be gen-
erated on a 0 to 1 transition of these bits.
f
f
f
f
VCO
VCO
PLL
PLL
= f
= f
= (PLLMUL+1)/(PLLDIV) • f
= 2*(PLLMUL+1) • f
PLL
D iv id e r
O u t p u t
D e t e c t o r
P L L M U L
VCO.
VCO
P h a s e
:
/ 2
.
P L L O P T
V C O
OSC
if PLLDIV = 0.
f
OSC
v c o
if PLLDIV > 0.
D e t e c t o r
1 / 2
L o c k
P L L O P T [ 1 ]
0
1
f
P L L
M a s k
AT32UC3A
VCO
L o c k b it
and the PLL
P L L c lo c k
57
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