ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 25

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

8.9
8.10
8052B–AVR–09/08
Clock Output
System Clock Prescaler
8-1 on page
shown in
Table 8-2.
Note:
The CPU clock divided by 2 can be output to the PB2 pin. The CPU can enable the clock out-
put function by setting the CKOE bit in the MCU Control Register. The clock will not run in any
sleep modes.
The ATmega4HVD/8HVD has a System Clock Prescaler, used to prescale the Calibrated Fast
RC Oscillator. The system clock can be divided by setting the
ister” on page
frequency as the requirement for power consumption and processing power changes. This
system clock will affect the clock frequency of the CPU and all synchronous peripherals. clk
clk
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher
than neither the clock frequency corresponding to the previous setting, nor the clock frequency
corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
may be faster than the CPU's clock frequency. It is not possible to determine the state of the
prescaler, and the exact time it takes to switch from one clock division to the other cannot be
exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and
T1 + 2*T2 before the new clock frequency is active. In this interval, two active clock edges are
produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new
prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
CPU
CLKPR to zero.
and clk
1. The actual value depends on the actual clock period of the Ultra Low Power RC Oscillator,
Table
refer to
23. The number of Ultra Low Power RC Oscillator cycles used for each time-out is
FLASH
Number of Ultra Low Power RC Oscillator Cycles
8-2.
29, and this enables the user to decrease or increase the system clock
Typ Time-out
”Ultra Low Power RC Oscillator” on page 24
are divided by a factor as shown in
128 ms
256 ms
512 ms
16 ms
32 ms
64 ms
4 ms
8 ms
(1)
ATmega4HVD/8HVD
Table 8-4 on page
for details.
”CLKPR – Clock Prescale Reg-
Number of Cycles
512
16K
32K
64K
1K
2K
4K
8K
30.
I/O
25
,