AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 159
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AT91SAM9261-CJ-999
Manufacturer Part Number
AT91SAM9261-CJ-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9261-CJ-999.pdf
(749 pages)
Specifications of AT91SAM9261-CJ-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
192K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
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Manufacturer
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21. Static Memory Controller (SMC)
21.1
21.2
Table 21-1.
21.3
Table 21-2.
6062M–ATARM–23-Mar-09
Name
NCS[7:0]
NRD
NWR0/NWE
A0/NBS0
NWR1/NBS1
A1/NWR2/NBS2
NWR3/NBS3
A[25:2]
D[31:0]
NWAIT
NWR0
A0
NWR1
A1
NWR3
Overview
I/O Lines Description
Multiplexed Signals
Multiplexed Signals
NWE
NBS0
NBS1
NWR2
NBS3
I/O Line Description
Static Memory Controller (SMC) Multiplexed Signals
Description
Static Memory Controller Chip Select Lines
Read Signal
Write 0/Write Enable Signal
Address Bit 0/Byte 0 Select Signal
Write 1/Byte 1 Select Signal
Address Bit 1/Write 2/Byte 2 Select Signal
Write 3/Byte 3 Select Signal
Address Bus
Data Bus
External Wait Signal
The Static Memory Controller (SMC) generates the signals that control the access to the exter-
nal memory devices or peripheral devices. It has 8 Chip Selects and a 26-bit address bus. The
32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate
read and write control signals allow for direct memory and peripheral interfacing. Read and write
signal waveforms are fully parametrizable.
The SMC can manage wait requests from external devices to extend the current access. The
SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from user-
programmed waveforms to slow-rate specific waveforms on read and write signals. The SMC
supports asynchronous burst read in page mode access for page size up to 32 bytes.
NBS2
Related Function
Byte-write or byte-select access, see
8-bit or 16-/32-bit data bus, see
Byte-write or byte-select access see
8-/16-bit or 32-bit data bus, see
Byte-write or byte-select access, see
Byte-write or byte-select access see
“Data Bus Width” on page 161
“Data Bus Width” on page
AT91SAM9261 Preliminary
“Byte Write or Byte Select Access” on page 161
“Byte Write or Byte Select Access” on page 161
“Byte Write or Byte Select Access” on page 161
“Byte Write or Byte Select Access” on page 161
161.
Output
Output
Output
Output
Output
Output
Output
Output
Type
Input
I/O
Active Level
Low
Low
Low
Low
Low
Low
Low
Low
159
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