AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 173
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AT91SAM9261-CJ-999
Manufacturer Part Number
AT91SAM9261-CJ-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9261-CJ-999.pdf
(749 pages)
Specifications of AT91SAM9261-CJ-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
192K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
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Manufacturer
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21.8.5
Table 21-4.
6062M–ATARM–23-Mar-09
Coded Value
setup [5:0]
pulse [6:0]
cycle [8:0]
Coding Timing Parameters
Coding and Range of Timing Parameters
Number of Bits
Figure 21-15. WRITE_MODE = 0. The write operation is controlled by NCS
All timing parameters are defined for one chip select and are grouped together in one
SMC_REGISTER according to their type.
The SMC_SETUP register groups the definition of all setup parameters:
• NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP
The SMC_PULSE register groups the definition of all pulse parameters:
• NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE
The SMC_CYCLE register groups the definition of all cycle parameters:
• NRD_CYCLE, NWE_CYCLE
Table 21-4
6
7
9
NWR0, NWR1,
NWR2, NWR3
NBS0, NBS1,
NBS2, NBS3,
A0, A1
D[31:0]
A
shows how the timing parameters are coded and their permitted range.
NWE,
[25:2]
MCK
NCS
256 x cycle[8:7] + cycle[6:0]
128 x setup[5] + setup[4:0]
256 x pulse[6] + pulse[5:0]
Effective Value
AT91SAM9261 Preliminary
Coded Value
0 ≤ ≤ 127
0 ≤ ≤ 31
0 ≤ ≤ 63
Permitted Range
Effective Value
0 ≤ ≤ 256+127
0 ≤ ≤ 512+127
0 ≤ ≤ 768+127
0 ≤ ≤ 128+31
0 ≤ ≤ 256+63
173
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