AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 47

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

11.3.9
11.3.10
6062M–ATARM–23-Mar-09
New ARM Instruction Set
Thumb Instruction Set Overview
Table 11-3.
Notes:
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
Table 11-4
Table 11-4.
Mnemonic
Mnemonic
MOV
ADD
SUB
CMP
TST
AND
EOR
• Branch instructions
• Data processing instructions
• Load and Store instructions
• Load and Store multiple instructions
• Exception-generating instruction
SMLAWy
SMULWy
SMULxy
SMLAxy
QDADD
QDSUB
SMLAL
BLX
QADD
QSUB
BXJ
1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
(1)
gives the Thumb instruction mnemonic list.
New ARM Instruction Mnemonic List
Thumb Instruction Mnemonic List
Operation
Move
Add
Subtract
Compare
Test
Logical AND
Logical Exclusive OR
Operation
Branch and exchange to Java
Branch, Link and exchange
Signed Multiply Accumulate 16
* 16 bit
Signed Multiply Accumulate
Long
Signed Multiply Accumulate 32
* 16 bit
Signed Multiply 16 * 16 bit
Signed Multiply 32 * 16 bit
Saturated Add
Saturated Add with Double
Saturated subtract
Saturated Subtract with double
AT91SAM9261 Preliminary
Mnemonic
Mnemonic
MVN
ADC
SBC
CMN
NEG
BIC
ORR
MRRC
MCRR
MCR2
CDP2
STRD
LDRD
BKPT
STC2
LDC2
PLD
CLZ
Store Double
Load Double
Operation
Move Not
Add with Carry
Subtract with Carry
Compare Negated
Negate
Bit Clear
Logical (inclusive) OR
Operation
Move double from coprocessor
Alternative move of ARM reg to
coprocessor
Move double to coprocessor
Alternative Coprocessor Data
Processing
Breakpoint
Soft Preload, Memory prepare
to load from address
Alternative Store from
Coprocessor
Coprocessor
Count Leading Zeroes
Alternative Load to
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