ADUC7032BSTZ-8V-RL Analog Devices Inc, ADUC7032BSTZ-8V-RL Datasheet - Page 116

• Manufacturer Part Number: ADUC7032BSTZ-8V-RL
• Description: IC BATTERY SENSOR PREC 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-8V-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: ADUC7032BSTZ-8V-RLCT

Preliminary Technical Data
LIN Hardware Synchronization Status Register :
Name :
Address :
Default Value :
Access :
Function :
Bit
7 - 6
5
4
3
2
1
0
Description
Reserved
These read-only bits are reserved for future use
LHS Reset Complete Flag
This bit is set to 1 by hardware to indicate a LHS Reset Command has completed successfully.
This bit is cleared to 0, after user code reads the LHSSTA MMR
Break Field Error
This bit is set to 1 by hardware and generates an LHS Interrupt (IRQEN[7]) when the 12-bit, Break Timer (LHSVAL1) register
overflows to indicate the LIN bus has stayed low too long thus indicating a possible LIN bus error.
This bit is cleared to 0, after user code reads the LHSSTA MMR
LHS Compare Interrupt
This bit is set to 1 by hardware when the value in LHSVAL0 (LIN Synchronisation Bit Timer) = the value in the LHSCMP
register.
This bit is cleared to 0, after user code reads the LHSSTA MMR
Stop Condition Interrupt
This bit is set to 1 by hardware when a stop condition is detected.
This bit is cleared to 0, after user code reads LHSSTA MMR
Start Condition Interrupt
This bit is set to 1 by hardware when a start condition is detected.
This bit is cleared to 0, after user code reads LHSSTA MMR
Break Timer Compare Interrupt
This bit is set to 1 by hardware when a valid LIN Break condition is detected. A LIN Break conditions is generated when
the LIN Break Timer value reaches the Break timer compare value (see LHSVAL1 description below).
This bit is cleared to 0, after user code reads the LHSSTA MMR
LHSSTA
0xFFFF0780
0x00
Read Only
The LHS Status register is an 8-bit register whose bits reflect the current operating status of the ADuC7032 LIN
interface.
Table 81 : LHSSTA MMR Bit Descriptions
Rev. PrD | Page 116 of 128
ADuC7032