UPSD3422E-40T6 STMicroelectronics, UPSD3422E-40T6 Datasheet - Page 149
UPSD3422E-40T6
Manufacturer Part Number
UPSD3422E-40T6
Description
MCU 8BIT 8032 64KB FLASH 52TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet
1.UPSD3422EV-40U6.pdf
(300 pages)
Specifications of UPSD3422E-40T6
Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
80KB (80K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-TQFP, 52-VQFP
For Use With
497-5577 - BOARD EVAL USB POWER SWITCH497-5518 - EVAL BOARD RFID READER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-4902
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPSD3422E-40T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
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- Download datasheet (3Mb)
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Table 94.
Table 95.
Table 96.
Bit 7
1-0
7-5
Bit
Bit
7
6
5
4
3
2
–
4
3
2
1
0
SPICLKD register bit definition
Not Used
SPISTAT: SPI interface status register (SFR D3h, reset value 02h)
SPISTAT register bit definition
RORISF
Symbol
Symbol
DIV128
DIV64
DIV32
DIV16
TEISF
BUSY
DIV8
DIV4
RISF
Bit 6
TISF
–
–
Bit 5
R/W
R/W
RW
RW
RW
RW
RW
RW
R
R
R
R
R
–
–
–
0 = No division
1 = Divide f
0 = No division
1 = Divide f
0 = No division
1 = Divide f
0 = No division
1 = Divide f
0 = No division
1 = Divide f
0 = No division
1 = Divide f
Reserved
SPI Busy
0 = Transmit or Receive is completed
1 = Transmit or Receive is in process
Transmission End Interrupt Source flag
0 = Automatically resets to '0' when firmware reads this
register
1 = Automatically sets to '1' when transmission end occurs
Receive Overrun Interrupt Source flag
0 = Automatically resets to '0' when firmware reads this
register
1 = Automatically sets to '1' when receive overrun occurs
Transfer Interrupt Source flag
0 = Automatically resets to '0' when SPITDR is full (just after
the SPITDR is written)
1 = Automatically sets to '1' when SPITDR is empty (just after
byte loads from SPITDR into SPI shift register)
Receive Interrupt Source flag
0 = Automatically resets to '0' when SPIRDR is empty (after
the SPIRDR is read)
1 = Automatically sets to '1' when SPIRDR is full
BUSY
Bit 4
OSC
OSC
OSC
OSC
OSC
OSC
TEISF
clock by 128
clock by 64
clock by 32
clock by 16
clock by 8
clock by 4
Bit 3
SPI (synchronous peripheral interface)
Definition
Definition
RORISF
Bit 2
TISF
Bit 1
RISF
Bit 0
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