MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 108
Manufacturer Part Number
IC MCU 2.1MHZ 15K OTP 52-PLCC
Specifications of MC68HC705B16CFN
Number Of I /o
Program Memory Size
15KB (15K x 8)
Program Memory Type
256 x 8
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
-40°C ~ 85°C
Package / Case
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
cannot be disabled by software (writing a ‘zero’ to the WDOG bit has no effect at any time). In
addition, the WDOG bit acts as a reset mechanism for the watchdog counter. Writing a ‘1’ to this
bit clears the counter to its initial value and prevents a watchdog timeout.
WDOG — Watchdog enable/disable
The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option.
Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified.
The divide-by-8 watchdog counter will generate a main reset of the chip when it reaches its final
state; seven clocks are necessary to bring the watchdog counter from its clear state to its final
state. This reset appears after time t
counter system. The watchdog counter, therefore, has to be cleared periodically, by software, with
a period less than t
The reset generated by the watchdog system is apparent at the RESET pin (see
RESET pin level is re-entered in the control logic, and when it has been maintained at level ‘zero’
for a minimum of t
The STOP instruction is inhibited when the watchdog system is enabled. If a STOP instruction is
executed while the watchdog system is enabled, then a watchdog reset will occur as if there were
a watchdog timeout. In the case of a watchdog reset due to a STOP instruction, the oscillator will
not be affected, thus there will be no t
configured according to the user specified mask option.
The state of the watchdog during WAIT mode is selected via a mask option (see
be one of the options below:
Watchdog enabled — the watchdog counter will continue to operate during WAIT mode and a
reset will occur after time t
Watchdog disabled — on entering WAIT mode, the watchdog counter system is reset and
disabled. On exiting WAIT mode the counter resumes normal operation.
0 (clear) –
COP watchdog during STOP mode
COP watchdog during WAIT mode
Watchdog enabled and counter cleared.
The watchdog cannot be disabled by software; writing a zero to this
bit has no effect.
, the RESET pin is released.
RESETS AND INTERRUPTS
since the last clear or since the enable of the watchdog
cycles start-up delay. On start-up, the watchdog will be