MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 113

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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9.2.3.2
Note:
INTP, INTN — External interrupt sensitivity options
These two bits allow the user to select which edge the IRQ pin is sensitive to as shown in
Table
external reset. Therefore the device is initialised with negative edge and low level sensitivity.
INTE — External interrupt enable
The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,
thus enabling the external interrupt function.
Table 9-3
to re-emphasize here that in order to avoid any conflict and spurious interrupt, it is only possible
to change the external interrupt options while the I-bit is set. Any attempt to change the external
interrupt option while the I-bit is clear will be unsuccessful. If an external interrupt is pending, it will
automatically be cleared when selecting a different interrupt option.
Note:
MC68HC05B6
Rev. 4.1
9-3. Both bits can be written to only while the I-bit is set, and are cleared by power-on or
1 (set)
0 (clear) –
Miscellaneous
describes the various triggering options available for the IRQ pin, however it is important
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in
If the external interrupt function is disabled by the INTE bit and an external interrupt is
sensed by the edge detector circuitry, then the interrupt request is latched and the
interrupt stays pending until the INTE bit is set. The internal latch of the external
interrupt is cleared in the first part of the service routine (except for the low level
Miscellaneous register
External interrupt function (IRQ) enabled.
External interrupt function (IRQ) disabled.
Section
INTP
0
0
1
1
Address
$000C
RESETS AND INTERRUPTS
INTN
3.8.
Table 9-3 IRQ sensitivity
0
1
0
1
POR
bit 7
Negative edge and low level sensitive
Negative edge only
Positive edge only
Positive and negative edge sensitive
INTP
bit 6
IRQ sensitivity
INTN
bit 5
INTE
bit 4
SFA
bit 3
bit 2
SFB
bit 1
SM
WDOG ?001 000?
bit 0
Freescale
on reset
State
9-9
9

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