MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 201

no-image

MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC705B16CFN
Manufacturer:
MOT
Quantity:
5 510
Part Number:
MC68HC705B16CFN
Manufacturer:
MOT
Quantity:
2 132
Company:
Part Number:
MC68HC705B16CFN
Manufacturer:
MOI
Quantity:
1 000
Part Number:
MC68HC705B16CFN
Manufacturer:
FREESCALE
Quantity:
1 402
Part Number:
MC68HC705B16CFNE
Manufacturer:
FREESCALE
Quantity:
2 512
E.4.1
If a non $00 byte is detected, the red LED is turned on and the routine stops (see
Figure
on. PD1 is then checked. If PD1=0, the bootstrap program stops here and no programming occurs
until such time as a high level is sensed on PD1. If PD1=1, the bootstrap program proceeds to
erase the EEPROM1 for a nominal 100 ms (4.0 MHz crystal). It is then checked for complete
erasure; if a non $FF byte is detected, the red LED is turned on, and erase is performed a second
time, and so on until total erasure is verified. At this point, both EPROM and EEPROM1 are
completely erased and the security bit is cleared. The programming operation can then be
performed. A schematic diagram of the circuit required for erased EPROM verification is shown in
Figure
E.4.2
Before the parallel bootstrap routines begin, the erased EPROM verification program is executed
as described in
the bootstrap program and verify for the EPROM taking approximately 15 seconds. The EPROM
is loaded in increasing address order with non EPROM segments being skipped by the loader.
Simultaneous programming is performed by reading eight bytes of data before actual
programming is performed, thus the loading time of the internal EPROM is divided by eight.
Parallel data is entered through Port A, while the 14-bit address is output on port B, PC0 to PC4
and TCMP2. If the data comes from an external EPROM, the handshake can be disabled by
connecting together PC5 and PC6. If the data is supplied by a parallel interface, handshaking will
be provided by PC5 and PC6 according to the timing diagram of
During programming, the green LED will flash at about 3 Hz.
Upon completion of the programming operation, the contents of the EPROM and EEPROM1 are
checked against the external data source. If programming is verified the green LED stays on, while
an error will cause the red LED to be turned on.
can be used to program the EPROM or to load and execute data in the RAM.
Note:
MC68HC05B6
Rev. 4.1
E-4). Only when the entire EPROM content is verified as erased does the green LED switch
E-7.
The entire EPROM and EEPROM1 can be loaded from the external source; if it is
desired to leave a segment undisturbed, the data for this segment should be all zeros
for EPROM data and all $FFs for EEPROM1 data.
Erased EPROM verification
EPROM/EEPROM parallel bootstrap
Section
E.4.1. When PD2=0, the programming time is set to 5 milliseconds with
MC68HC705B16
Figure E-7
is a schematic diagram of a circuit that
Figure E-5
(see also
Figure E-3
Figure
Freescale
E-6).
E-13
and
14

Related parts for MC68HC705B16CFN