MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 123

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

4.5.3.2 Show Cycle Strobe (SHS)
4.5.3.3 Transfer Acknowledge (TA)
4.5.3.4 Transfer Error Acknowledge (TEA)
4.5.3.5 Emulation Mode Chip Selects (CSE[1:0])
4.5.3.6 Transfer Code (TC[2:0])
4.5.3.7 Read/Write (R/W)
MMC2107 – Rev. 2.0
MOTOROLA
NOTE:
This output signal is used in emulation mode as a strobe for capturing
addresses, controls, and data during show cycles. This signal is also
used as RCON.
This input signal, used only during reset, indicates whether the states on
the external signals affect the chip configuration.
This signal indicates that the external data transfer is complete. During
a read cycle, when the processor recognizes TA, it latches the data and
then terminates the bus cycle. During a write cycle, when the processor
recognizes TA, the bus cycle is terminated. This signal is an input in
master and emulation modes.
This signal indicates an error condition exists for the bus transfer. The
bus cycle is terminated and the central processor unit (CPU) begins
execution of the access error exception. This signal is an input in master
and emulation modes.
These output signals provide information for development support.
These output signals indicate the data transfer code for the current bus
cycle.
This output signal indicates the direction of the data transfer on the bus.
A logic 1 indicates a read from a slave device and a logic 0 indicates a
write to a slave device.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Signal Description
Signal Descriptions
Signal Description
Technical Data
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