MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 138

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Reset Controller Module
5.7.1.5 Loss of Lock Reset
5.7.1.6 Software Reset
5.7.2 Reset Control Flow
5.7.2.1 Synchronous Reset Requests
Technical Data
138
This reset condition occurs in PLL clock mode when the LOLRE bit in
SYNCR is set and the PLL loses lock. The reset controller asserts
RSTOUT for approximately 512 cycles after the PLL has acquired lock.
The part then exits reset and begins operation.
A software reset occurs when the SOFTRST bit is set. If the RESET pin
is negated and the PLL has acquired lock, the reset controller asserts
RSTOUT for approximately 512 cycles. Then the part exits reset and
begins operation.
Figure 5-5
follows, there are references in parentheses to the control state box
numbers in the figure. All cycle counts given are approximate.
If either the external RESET pin is asserted by an external device for at
least four rising CLKOUT edges (3), or the watchdog timer times out, or
software requests a reset, the reset control logic latches the reset
request internally and enables the bus monitor (5). When the current bus
cycle is completed (6), RSTOUT is asserted (7). The reset control logic
waits until the RESET pin is negated (8) and for the PLL to attain lock
(9, 9A) before waiting 512 CLKOUT cycles (10). The reset control logic
may latch the configuration according to the RCON pin level (11, 11A)
before negating RSTOUT (12).
If the external RESET pin is asserted by an external device for at least
four rising CLKOUT edges during the 512 count (10) or during the wait
for PLL lock (9A), the reset flow switches to (8) and waits for the RESET
pin to be negated before continuing.
Freescale Semiconductor, Inc.
For More Information On This Product,
shows the reset logic control flow. In the flow description that
Go to: www.freescale.com
Reset Controller Module
MMC2107 – Rev. 2.0
MOTOROLA