MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 168

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Interrupt Controller Module
7.8.1 Interrupt Sources and Prioritization
7.8.2 Fast and Normal Interrupt Requests
Technical Data
168
Each interrupt source in the system sends a unique signal to the interrupt
controller. Up to 40 interrupt sources are supported. Each interrupt
source can be programmed to one of 32 priority levels using PLSR in the
interrupt controller. The highest priority level is 31 and lowest priority
level is 0. By default, each interrupt source is assigned to the priority
level 0. Each interrupt source is associated with a 5-bit priority level
select value that selects one of 32 priority levels. The interrupt controller
uses the priority levels as the basis for the generation of all interrupt
signals to the M•CORE processor.
Interrupt requests may be forced by software by writing to IFRH and
IFRL. Each bit of IFRH and IFRL is logically ORed with the
corresponding interrupt source signal before the priority level select
logic. To negate the forced interrupt request, the interrupt handler can
clear the appropriate IFR bit. IPR reflects the state of each priority level.
FIER allows individual enabling or masking of pending fast interrupt
requests. FIER is logically ANDed with IPR, and the result is stored in
FIPR. FIPR bits are bit-wise ORed together and inverted to form the fast
interrupt signal routed to the M•CORE processor. The FIPR allows
software to quickly determine the highest priority pending fast interrupt.
The output of FIPR also feeds into a 32-to-5 priority encoder to generate
the vector number to present to the M•CORE processor if vectored
interrupts are required.
NIER allows individual enabling or masking of pending normal interrupt
requests. NIER is logically ANDed with IPR, and the result is stored in
NIPR. NIPR bits are bit-wise ORed together and inverted to form the
normal interrupt signal routed to the M•CORE processor. The normal
interrupt signal is only asserted if the fast interrupt signal is negated. The
NIPR allows software to quickly determine the highest priority pending
normal interrupt. The output of NIPR also feeds into a 32-to-5 priority
encoder to generate the vector number to present to the M•CORE
processor if vectored interrupts are required. If the fast interrupt signal is
asserted, then the vector number is determined by the highest priority
fast interrupt.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Interrupt Controller Module
MMC2107 – Rev. 2.0
MOTOROLA