MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 169

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

7.8.3 Autovectored and Vectored Interrupt Requests
MMC2107 – Rev. 2.0
MOTOROLA
If an interrupt is pending at a given priority level and both the
corresponding FIER and NIER bits are set, then both the corresponding
FIPR and NIPR bits are set, assuming these bits are not masked.
Fast interrupt requests always have priority over normal interrupt
requests, even if the normal interrupt request is at a higher priority level
than the highest fast interrupt request.
If the fast interrupt signal is asserted when the normal interrupt signal is
already asserted, then the normal interrupt signal is negated.
IPR, NIPR, and FIPR are read-only. To clear a pending interrupt, the
interrupt must be cleared at the source using a special clearing
sequence defined by each source. All interrupt sources to the interrupt
controller are to be held until recognized and cleared by the interrupt
service routine. The interrupt controller does not have any edge-detect
logic. Edge-triggered interrupt sources are handled at the source
module.
In ICR, the MASK[4:0] bits can mask interrupt sources at and below a
selected priority level. The MFI bit determines whether the mask applies
only to normal interrupts or to fast interrupts with all normal interrupts
being masked. The ME bit enables interrupt masking.
ISR reflects the current vector number and the states of the signals to
the M•CORE processor.
The vector number and fast/normal interrupt sources are synchronized
before being sent to the M•CORE processor. Thus, the interrupt
controller adds one clock of latency to the interrupt sequence. The fast
and normal interrupt raw sources are not synchronized to allow these
signals to be used to wake up the M•CORE processor during stop mode
when all system clocks are stopped.
The AE bit in ICR enables autovectored interrupt requests to the
M•CORE processor. AE is set by default, and all interrupt requests are
autovectored. An interrupt handler may read FIPR or NIPR to determine
the priority of the interrupt source. If multiple interrupt sources share the
same priority level, then it is up to the interrupt service routine to
determine the correct source of the interrupt.
Freescale Semiconductor, Inc.
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Interrupt Controller Module
Interrupt Controller Module
Functional Description
Technical Data
169