MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 189

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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MMC2107 – Rev. 2.0
MOTOROLA
FSTOP — FLASH Stop Enable Bit
FDBG — FLASH Debug Enable Bit
EME — Emulation Enable Bit
SIE — Shadow Information Enable Bit
The read-always FSTOP bit causes the CMFR to enter a low-power
stop mode. Writing has no effect if SES = 1. When FSTOP is set, the
BIU continues to operate to allow accesses to CMFRMCR. Accesses
to other registers are terminated with bus error. Accesses to the array
are ignored. To prevent unpredictable behavior, change the FSTOP
bit in a separate write operation.
The read/write FDBG bit determines whether the set-once LOCKCTL
bit is writable when the chip is in debug mode. Writing to the FDBG bit
must occur before the LOCKCTL bit is writable.
The read-always EME bit enables the CMFR to enter emulation
mode. EME is writable when the LOCKCTL and DIS bits are set.
During emulation mode the CMFR terminates array access cycles,
but does not drive data. Array data can be emulated by reading an
external memory, and on-page/off-page timing is the same as in
non-emulation mode. Note that write accesses to the array space are
the same as normal mode.
For more information about emulation operation see
Operation.
The read-always SIE bit selects the shadow information row. SIE is
write-protected when the ERASE bit is clear and the SES bit is set.
When SIE is set and an array location is read using supervisor data,
the shadow information is read from a location determined by the
column, 32 byte read page select, and word addresses of the access.
Accessing the control block registers accesses the registers and not
the shadow information.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = CMFR in low-power stop mode
0 = CMFR in normal mode
1 = Debug mode enabled
0 = Debug mode disabled
1 = Emulation mode enabled
0 = Emulation mode disabled
1 = Shadow information enabled; normal array access disabled
0 = Shadow information disabled; normal array access enabled
Non-Volatile Memory FLASH (CMFR)
Go to: www.freescale.com
Non-Volatile Memory FLASH (CMFR)
Registers and Memory Map
9.8.7 Emulation
Technical Data
189

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