MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 205

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

9.8 Functional Description
9.8.1 Master Reset
9.8.2 Register Read and Write Operation
9.8.3 Array Read Operation
MMC2107 – Rev. 2.0
MOTOROLA
The CMFR is an electrically erasable and programmable non-volatile
memory. This subsection describes the functioning of the CMFR during
various operational modes.
The device signals a master reset to the CMFR when a full reset is
required. A master reset is the highest priority operation for the CMFR
and terminates all other operations. The CMFR uses master reset to
initialize all register bits to their default reset value. If the CMFR is in
program or erase operation (EHV = 1) and a master reset is generated,
the module performs the needed interlocks to disable the high voltage
without damage to the high voltage circuits. Master reset terminates any
other mode of operation and forces the CMFR BIU to a state ready to
receive accesses.
The CMFR control registers are accessible for read or write operation at
all times while the device is powered up except during master reset.
The access time of a CMFR register is one system clock for both read
and write accesses. Accesses to unimplemented registers causes the
BIU to generate a data error exception.
The CMFR array is available for read operation under most conditions
while the device is powered up. Reads of the array are ignored (no
response) during master reset or while the CMFR is disabled or in stop
mode. During programming and erase operation while the high voltage
is applied to the array (EHV = 1 or HVS = 1) the BIU generates data
errors for all array accesses. At certain points, as defined in the program
or erase sequence, reading the array results in a margin read. These
margin reads return the status of the program or erase operation and not
the data in the array.
Freescale Semiconductor, Inc.
For More Information On This Product,
Non-Volatile Memory FLASH (CMFR)
Go to: www.freescale.com
Non-Volatile Memory FLASH (CMFR)
Functional Description
Technical Data
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