MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 206

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Non-Volatile Memory FLASH (CMFR)
9.8.4 Programming
Technical Data
206
CAUTION:
NOTE:
The type of array read is determined by comparing the address of the
requested information with the address of the read page buffers. If the
requested address is not in one of the read page buffers or if the read
page buffer has been made invalid, an off-page read results. This read
updates the selected array block’s read page buffer address, copies the
information from the array into the read page buffer, and drives a
word/half-word onto the data bus. The off-page read requires a minimum
of two clocks; margin off-page reads require additional clocks (see
9.8.4.2 Program Margin Reads
the address of the requested information is within the address ranges of
either of the read page buffers, the second type of read is performed.
This read is an on-page read and requires one clock to transfer
information from the read page buffer onto the data bus.
After reset, programming writes, erase interlock write, setting EHV,
clearing SES, setting/clearing SIE and exiting stop mode or disable
mode, the page buffers do not contain valid information and the CMFR
must do an off-page read before an on-page read can be done.
To modify the charge stored in the isolated element of the CMFR bit from
a logic 1 state to a logic 0 state, a programming operation is required. A
programmed bit reads as logic 0. This programming operation applies
the required voltages to change the charge state of the selected bits
without changing the logic state of any other bits in the array. The
program operation cannot change the logic 0 state to a logic 1 state; this
transition must be done by the erase operation. An erased bit reads as
logic 1. Programming uses a set of eight program buffers of 64 bytes to
store the required data, an address offset buffer to store the starting
address of the block(s) to be programmed, and a block select buffer that
stores information on which block(s) are to be programmed. From one to
eight of the program page buffers may be programmed at one time.
Do not program any page more than once after a successful erase
operation. While this does not physically damage the array it causes an
increased partial disturb time for the unselected bits on the row and
columns that are not programmed. A full erase of all blocks being
programmed must be done before the CMFR can be used reliably.
Freescale Semiconductor, Inc.
For More Information On This Product,
Non-Volatile Memory FLASH (CMFR)
Go to: www.freescale.com
and
9.8.5.2 Erase Margin
MMC2107 – Rev. 2.0
Reads). If
MOTOROLA