MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 218

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Non-Volatile Memory FLASH (CMFR)
9.8.5.2 Erase Margin Reads
Technical Data
218
State
S3
S4
S5
High voltage write enable: Erase margin
Erase operation: High voltage applied to
Erase margin read operation: Reads
reads occur. CMFR accepts erase hardware
interlock write. Normal register accesses
(except CMFRMCR). CMFRMCR write
causes NVM fuses to be cleared during the
high-voltage pulse. If CMFRMCR was
written, a CMFRMCR read returns the NVM
fuses value. CMFRCTL write can change
EHV. When HVS goes high, NVR and
PAWS are locked.
array blocks to erase bitcells. Pulse-width
timer active if SCLKR[2:0]
polled to time the erase pulse. During erase,
array cannot be accessed (bus error).
Normal register accesses. CMFRCTL write
can change only EHV.
determine if bits in selected blocks need
modification by the erase operation. Erased
bit reads as 1. All words in erased blocks
must be read to determine if erase is
complete.
Table 9-10 Erase Interlock State Descriptions (Continued)
Mode
The CMFR provides an erase margin read with electrical margin for the
erase state. Erase margin reads provide sufficient margin to assure
specified data retention. The erase margin read is enabled when
SES = 1 and the erase write has occurred. The erase margin read and
subsequent on-page erase verify reads return a 0 for any bit that has not
completely erased. Bits that have completed erasing read as a 1s. To
increase the access time of the erase margin read, the off-page access
time is 17 clocks instead of the usual 2-clock off-page read access time.
The erase margin read occurs while doing an off-page read. All locations
within the block(s) that are being erased must read as a 1 to determine
that no more erase pulses are required.
Freescale Semiconductor, Inc.
For More Information On This Product,
Non-Volatile Memory FLASH (CMFR)
0; HVS can be
Go to: www.freescale.com
State
Next
S1
S4
S1
S5
S4
S1
T6 Write SES = 0 or a master reset
T4 Write EHV = 1
T7 Master reset
T5 EHV = 0 and HVS = 0
T8 Write EHV = 1
T9 Write SES = 0 or a master reset
Transition Requirement
MMC2107 – Rev. 2.0
MOTOROLA