MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 224

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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Clock Module
10.4.4.2 Stop Mode
10.5 Block Diagram
Technical Data
224
EXTAL
OSCILLATOR
XTAL
In stop mode, all system clocks are disabled. There are several options
for enabling/disabling the PLL and/or crystal oscillator in stop mode at
the price of increased wakeup recovery time. The PLL can be disabled
in stop mode, but then it requires a wakeup period before it can relock.
The OSC can also be disabled during stop mode, but then it requires a
wakeup period to restart.
When the PLL is enabled in stop mode (STPMD[1:0]), the external
CLKOUT signal can support systems using CLKOUT as the clock
source.
There is also a fast wakeup option for quickly enabling the system clocks
during stop recovery. This eliminates the wakeup recovery time but at a
price of sending a potentially unstable clock to the system. To prevent a
non-locked PLL frequency overshoot when using the fast wakeup
option, change the RFD divisor to the current RFD value plus one before
entering stop mode.
In external clock mode, there are no wakeup periods for oscillator startup
or PLL lock.
Figure 10-1. Clock Module Block Diagram
Freescale Semiconductor, Inc.
REFERENCE CLOCK
For More Information On This Product,
Go to: www.freescale.com
V
DDSYN
Clock Module
CLKGEN
DISCLK
V
SSSYN
PLL
RSTOUT
VCO CLKOUT
INTERNAL CLOCKS
MMC2107 – Rev. 2.0
RFD
MOTOROLA
CLKOUT

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