MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 231

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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MMC2107 – Rev. 2.0
MOTOROLA
PLLMODE — Clock Mode Bit
PLLSEL — PLL Select Bit
PLLREF — PLL Reference Bit
LOCKS — Sticky PLL Lock Bit
The MODE bit is configured at reset and reflects the clock mode as
shown in
The PLLSEL bit is configured at reset and reflects the PLL mode as
shown in
The PLLREF bit is configured at reset and reflects the PLL reference
source in normal PLL mode as shown in
The LOCKS flag is a sticky indication of PLL lock status.
The lock detect function sets the LOCKS bit when the PLL achieves
lock after:
When the PLL loses lock, LOCKS is cleared. When the PLL relocks,
LOCKS remains cleared until one of the two listed events occurs.
Freescale Semiconductor, Inc.
MODE:PLLSEL:PLLREF
For More Information On This Product,
1 = PLL clock mode
0 = External clock mode
1 = Normal PLL mode
0 = 1:1 PLL mode
1 = Crystal clock reference
0 = External clock reference
1 = No unintentional PLL loss of lock since last system reset or
0 = PLL loss of lock since last system reset or MFD change or
– A system reset, or
– A write to SYNCR that changes the MFD[2:0] bits
MFD change
currently not locked due to exit from STOP with FWKUP set
Table
Table
Go to: www.freescale.com
000
100
110
111
Table 10-5. System Clock Modes
Clock Module
10-5.
10-5.
External clock mode
1:1 PLL mode
Normal PLL mode with external clock reference
Normal PLL mode with crystal oscillator
reference
Clock Mode
Table
Memory Map and Registers
10-5.
Technical Data
Clock Module
231

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