MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 236

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Clock Module
10.8.2 System Clocks Generation
10.8.3 PLL Lock Detection
Technical Data
236
NOTE:
In normal PLL clock mode, the default system frequency is two times the
reference frequency after reset. The RFD[2:0] and MFD[2:0] bits in
SYNCR select the frequency multiplier.
When programming the PLL, do not exceed the maximum system clock
frequency listed in the electrical specifications. Use this procedure to
accommodate the frequency overshoot that occurs when the MFD bits
are changed:
Keep the maximum system clock frequency below the limit given in
Section 22. Electrical
The lock detect logic monitors the reference frequency and the PLL
feedback frequency to determine when frequency lock is achieved.
Phase lock is inferred by the frequency relationship, but is not
guaranteed. The LOCK flag in SYNSR reflects the PLL lock status. A
sticky lock flag, LOCKS, is also provided.
The lock detect function uses two counters. One is clocked by the
reference and the other is clocked by the PLL feedback. When the
reference counter has counted N cycles, its count is compared to that of
the feedback counter. If the feedback counter has also counted N cycles,
the process is repeated for N + K counts. Then, if the two counters still
match, the lock criteria is relaxed by 1/2 and the system is notified that
the PLL has achieved frequency lock.
1. Determine the appropriate value for the MFD and RFD fields in
2. Write a value of RFD (from step 1) + 1 to the RFD field of SYNCR.
3. Write the MFD value from step 1 to SYNCR.
4. Monitor the LOCK flag in SYNSR. When the PLL achieves lock,
Freescale Semiconductor, Inc.
For More Information On This Product,
SYNCR. The amount of jitter in the system clocks can be
minimized by selecting the maximum MFD factor that can be
paired with an RFD factor to provide the required frequency.
write the RFD value from step 1 to the RFD field of SYNCR. This
changes the system clocks frequency to the required frequency.
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Clock Module
Specifications.
MMC2107 – Rev. 2.0
MOTOROLA