MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 238

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Clock Module
10.8.3.1 PLL Loss of Lock Conditions
10.8.3.2 PLL Loss of Lock Reset
10.8.4 Loss of Clock Detection
Technical Data
238
NOTE:
Once the PLL acquires lock after reset, the LOCK and LOCKS flags are
set. If the MFD is changed, or if an unexpected loss of lock condition
occurs, the LOCK and LOCKS flags are negated. While the PLL is in the
non-locked condition, the system clocks continue to be sourced from the
PLL as the PLL attempts to relock. Consequently, during the relocking
process, the system clocks frequency is not well defined and may
exceed the maximum system frequency, violating the system clock
timing specifications.
However, once the PLL has relocked, the LOCK flag is set. The LOCKS
flag remains cleared if the loss of lock is unexpected. The LOCKS flag is
set when the loss of lock is caused by changing MFD. If the PLL is
intentionally disabled during stop mode, then after exit from stop mode,
the LOCKS flag reflects the value prior to entering stop mode once lock
is regained.
If the LOLRE bit in SYNCR is set, a loss of lock condition asserts reset.
Reset reinitializes the LOCK and LOCKS flags. Therefore, software
must read the LOL bit in reset status register (RSR) to determine if a loss
of lock caused the reset. See
To exit reset in PLL mode, the reference must be present, and the PLL
must achieve lock.
In external clock mode, the PLL cannot lock. Therefore, a loss of lock
condition cannot occur, and the LOLRE bit has no effect.
The LOCEN bit in SYNCR enables the loss of clock detection circuit to
monitor the input clocks to the phase and frequency detector (PFD).
When either the reference or feedback clock frequency falls below the
minimum frequency, the loss of clock circuit sets the sticky LOCS flag in
SYNSR.
In external clock mode, the loss of clock circuit is disabled.
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Clock Module
5.6.2 Reset Status
Register.
MMC2107 – Rev. 2.0
MOTOROLA