MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 239

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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10.8.4.1 Alternate Clock Selection
MMC2107 – Rev. 2.0
MOTOROLA
Depending on which clock source fails, the loss-of-clock circuit switches
the system clocks source to the remaining operational clock. The
alternate clock source generates the system clocks until reset is
asserted. As
of lock and into self-clocked mode (SCM). The PLL remains in SCM until
the next reset. When the PLL is operating in SCM, the system frequency
depends on the value in the RFD field. The SCM system frequency
stated in electrical specifications assumes that the RFD has been
programmed to binary 000. If the loss-of-clock condition is due to PLL
failure, the PLL reference becomes the system clocks source until the
next reset, even if the PLL regains and relocks.
A special loss-of-clock condition occurs when both the reference and the
PLL fail. The failures may be simultaneous, or the PLL may fail first. In
either case, the reference clock failure takes priority and the PLL
attempts to operate in SCM. If successful, the PLL remains in SCM until
the next reset. If the PLL cannot operate in SCM, the system remains
static until the next reset. Both the reference and the PLL must be
functioning properly to exit reset.
1. The LOC circuit monitors the reference and feedback inputs to the PFD. See
External
Clock
Freescale Semiconductor, Inc.
Mode
PLL
For More Information On This Product,
Go to: www.freescale.com
Before Failure
System Clock
Table 10-7
External clock
Source
Table 10-7. Loss of Clock Summary
PLL
Clock Module
shows, if the reference fails, the PLL goes out
PLL self-clocked mode
Circuit
Reference Failure
Selected by LOC
Alternate Clock
(1)
None
Until Reset
Functional Description
Alternate Clock
PLL reference
Selected by
LOC Circuit
PLL Failure
Until Reset
Technical Data
Clock Module
NA
Figure
10-8.
239

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