MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 322
MMC2107CFCPV33
Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet
1.MMC2107CFCAF33.pdf
(618 pages)
Specifications of MMC2107CFCPV33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Timer Modules (TIM1 and TIM2)
15.8.3 Output Compare
Technical Data
322
Pin conditions such as rising or falling edges can trigger an input capture
only on a pin configured as an input.
An input capture on channel x sets the CxF flag. The CxI bit enables the
CxF flag to generate interrupt requests.
Setting an I/O select bit, IOSx, configures channel x as an output
compare channel. The output compare function can generate a periodic
pulse with a programmable polarity, duration, and frequency. When the
timer counter reaches the value in the channel registers of an output
compare channel, the timer can set, clear, or toggle the channel pin. An
output compare on channel x sets the CxF flag. The CxI bit enables the
CxF flag to generate interrupt requests.
The output mode and level bits, OMx and OLx, select, set, clear, or
toggle on output compare. Clearing both OMx and OLx disconnects the
pin from the output logic.
Setting a force output compare bit, FOCx, causes an output compare on
channel x. A forced output compare does not set the channel flag.
A successful output compare on channel 3 overrides output compares
on all other output compare channels. A channel 3 output compare can
cause bits in the output compare 3 data register to transfer to the timer
port data register, depending on the output compare 3 mask register.
The output compare 3 mask register masks the bits in the output
compare 3 data register. The timer counter reset enable bit, TCRE,
enables channel 3 output compares to reset the timer counter. A channel
3 output compare can reset the timer counter even if the OC3/PAI pin is
being used as the pulse accumulator input.
An output compare overrides the data direction bit of the output compare
pin but does not change the state of the data direction bit.
Writing to the timer port bit of an output compare pin does not affect the
pin state. The value written is stored in an internal latch. When the pin
becomes available for general-purpose output, the last value written to
the bit appears at the pin.
Freescale Semiconductor, Inc.
For More Information On This Product,
Timer Modules (TIM1 and TIM2)
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA
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