MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 342

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Serial Communications Interface Modules (SCI1 and SCI2)
16.7.4 SCI Status Register 1
Technical Data
342
Address: SCI1 — 0x00cc_0004
Serial Communications Interface Modules (SCI1 and SCI2)
Reset:
Read: Anytime
Write: Has no meaning or effect
TDRE — Transmit Data Register Empty Flag
TC — Transmit Complete Flag
Read:
Write:
The TDRE flag is set when the transmit shift register receives a word
from the SCI data register. It signals that the SCIDRH and SCIDRL
are empty and can receive new data to transmit. If the TIE bit in the
SCICR2 is also set, TDRE generates an interrupt request. Clear
TDRE by reading SCISR1 and then writing to SCIDRL. Reset sets
TDRE.
The TC flag is set when TDRE = 1 and no data, preamble, or break
frame is being transmitted. It signals that no transmission is in
progress. If the TCIE bit is set in SCICR2, TC generates an interrupt
request. When TC is set, the TXD pin is idle (logic 1). TC is cleared
automatically when a data, preamble, or break frame is queued. Clear
TC by reading SCISR1 with TC set and then writing to SCIDRL. TC
cannot be cleared while a transmission is in progress. Reset sets TC.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Transmit data register empty
0 = Transmit data register not empty
1 = No transmission in progress
0 = Transmission in progress
SCI2 — 0x00cd_0004
TDRE
Bit 7
1
Figure 16-6. SCI Status Register 1 (SCISR1)
Go to: www.freescale.com
= Writes have no effect and the access terminates without a transfer error exception.
TC
6
1
RDRF
5
0
IDLE
4
0
OR
3
0
NF
2
0
MMC2107 – Rev. 2.0
FE
1
0
MOTOROLA
Bit 0
PF
0