MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 354

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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Serial Communications Interface Modules (SCI1 and SCI2)
Technical Data
354
NOTE:
Serial Communications Interface Modules (SCI1 and SCI2)
The SCI sets the TDRE flag every time it transfers data from SCIDRH
and SCIDRL to the transmit shift register. TDRE indicates that SCIDRH
and SCIDRL can accept new data. If the TIE bit is set, TDRE generates
an interrupt request.
SCIDRH and SCIDRL transfer data to the transmit shift register and sets
TDRE 9/16ths of a bit time after the previous frame’s stop bit starts to
shift out.
Hardware supports odd or even parity. When parity is enabled, the most
significant data bit is the parity bit.
When the transmit shift register is not transmitting a frame, the TXD pin
goes to the idle condition, logic 1. Clearing the TE bit while the
transmitter is idle will return control of the TXD pin to the SCI data
direction (SCIDDR) and SCI port (SCIPORT) registers.
If the TE bit is cleared while a transmission is in progress (while TC = 0),
the frame in the transmit shift register continues to shift out. Then the
TXD pin reverts to being a general-purpose I/O pin even if there is data
pending in the SCI data register. To avoid accidentally cutting off a
message, always wait until TDRE is set after the last frame before
clearing TE.
To separate messages with preambles with minimum idle line time, use
this sequence between messages:
When the SCI relinquishes the TXD pin, the SCIPORT and SCIDDR
registers control the TXD pin.
To force TXD high when turning off the transmitter, set bit 1 of the SCI
port register (SCIPORT) and bit 1 of the SCI data direction register
(SCIDDR). The TXD pin goes high as soon as the SCI relinquishes
control of it.
1. Write the last byte of the first message to SCIDRH and SCIDRL.
2. Wait until the TDRE flag is set, indicating the transfer of the last
3. Queue a preamble by clearing and then setting the TE bit.
4. Write the first byte of the second message to SCIDRH and
Freescale Semiconductor, Inc.
For More Information On This Product,
frame to the transmit shift register.
SCIDRL.
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA

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