MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 363

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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16.12.5.1 Slow Data Tolerance
MMC2107 – Rev. 2.0
MOTOROLA
Serial Communications Interface Modules (SCI1 and SCI2)
Figure 16-23
without causing a noise error or a framing error. The slow stop bit begins
at RT8 instead of RT1 but arrives in time for the stop bit data samples at
RT8, RT9, and RT10.
For 8-bit data, sampling of the stop bit takes the receiver:
With the misaligned data shown in
154 RT cycles at the point when the count of the transmitting device is:
The maximum percent difference between the receiver count and the
transmitter count for slow 8-bit data with no errors is:
For 9-bit data, sampling of the stop bit takes the receiver:
With the misaligned data shown in
170 RT cycles at the point when the count of the transmitting device is:
The maximum percent difference between the receiver count and the
transmitter count for slow 9-bit data with no errors is:
Freescale Semiconductor, Inc.
RECEIVER
RT CLOCK
For More Information On This Product,
10 bit times
9 bit times
10 bit times
9 bit times
Go to: www.freescale.com
shows how much a slow received frame can be misaligned
16 RT cycles + 10 RT cycles = 154 RT cycles.
16 RT cycles + 3 RT cycles = 147 RT cycles.
16 RT cycles + 10 RT cycles = 170 RT cycles.
16 RT cycles + 3 RT cycles = 163 RT cycles.
MSB
Serial Communications Interface Modules (SCI1 and SCI2)
154 147
------------------------- -
170 163
------------------------- -
Figure 16-23. Slow Data
154
170
Figure
Figure
100
100
SAMPLES
DATA
=
=
16-23, the receiver counts
16-23, the receiver counts
4.54%
4.12%
STOP
Technical Data
Receiver
363

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