MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 365

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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16.12.6 Receiver Wakeup
16.12.6.1 Idle Input Line Wakeup (WAKE = 0)
16.12.6.2 Address Mark Wakeup (WAKE = 1)
MMC2107 – Rev. 2.0
MOTOROLA
Serial Communications Interface Modules (SCI1 and SCI2)
So that the SCI can ignore transmissions intended only for other devices
in multiple-receiver systems, the receiver can be put into a standby
state. Setting the RWU bit in SCICR2 puts the receiver into a standby
state during which receiver interrupts are disabled.
The transmitting device can address messages to selected receivers by
including addressing information in the initial frame or frames of each
message.
The WAKE bit in SCICR1 determines how the SCI is brought out of the
standby state to process an incoming message. The WAKE bit enables
either idle line wakeup or address mark wakeup.
When WAKE = 0, an idle condition on the RXD pin clears the RWU bit
and wakes up the receiver. The initial frame or frames of every message
contain addressing information. All receivers evaluate the addressing
information, and receivers for which the message is addressed process
the frames that follow. Any receiver for which a message is not
addressed can set its RWU bit and return to the standby state. The RWU
bit remains set and the receiver remains on standby until another idle
frame appears on the RXD pin.
Idle line wakeup requires that messages be separated by at least one
idle frame and that no message contains idle frames.
The idle frame that wakes up the receiver does not set the IDLE flag or
the RDRF flag.
The ILT bit in SCICR1 determines whether the receiver begins counting
logic 1s as idle frame bits after the start bit or after the stop bit.
When WAKE = 1, an address mark clears the RWU bit and wakes up the
receiver. An address mark is a 1 in the most significant data bit position.
The receiver interprets the data as address data. When using address
mark wakeup, the MSB of all non-address data must be 0. User code
must compare the address data to the receiver’s address and, if the
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Serial Communications Interface Modules (SCI1 and SCI2)
Technical Data
Receiver
365

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