MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 405

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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18.5.2 Stop Mode
18.6 Signals
MMC2107 – Rev. 2.0
MOTOROLA
The QADC enters a low-power idle state whenever the QSTOP bit is set
or the part is in stop mode.
QADC stop:
Because the bias currents to the analog circuit are turned off in stop, the
QADC requires some recovery time (t
The QADC uses the external pins shown in
channel/port pins that can support up to 18 channels when external
multiplexing is used (including internal channels). All of the channel pins
can also be used as general-purpose digital port pins. In addition, there
are also two analog reference pins and two analog submodule power
pins.
The QADC has external trigger inputs and the multiplexer outputs
combined onto some of the channel pins.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Disables the analog-to-digital converter, effectively turning off the
analog circuit.
Aborts the conversion sequence in progress
Changes the data direction register (DDRQA), port data registers
(PORTQA and PORTQB), control registers (QACR2, QACR1, and
QACR0) and the status registers (QASR1 and QASR0) to
read-only. Only the module configuration register (QADCMCR) is
writable.
Causes the RAM to not be accessible, can not read valid results
from RAM (result word table and CCW) nor write to the RAM
(result word table and CCW).
Resets QACR1, QACR2, QASR0, and QASR1
Holds the QADC periodic/interval timer in reset
Go to: www.freescale.com
Queued Analog-to-Digital Converter (QADC)
SR
) to stabilize the analog circuits.
Figure
18-2. There are eight
Technical Data
Signals
405

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